Semiconductor graphics memory devices used in liquid crystal display (LCD) products, such as a super twisted nematic (STN) thin film transistor (TFT) LCD that employs an LCD driver integrated circuit (LDI), are of a dual-port type that can perform a read/write operation through one port and a read operation through the other port. These semiconductor graphics memory devices are classified into a 6T type, a 7T type, a 8T type, based on the number of MOS field effect transistors (MOSFET) included in each bit cell. Because the 6T-type has fewer transistors that the 7T-type or 8T-type transistors, it has an advantage of being realized in a smaller chip size. Because of its smaller size advantage, the 6T type semiconductor memory device is generally used in color LDI products that require high density.
This 6T-type semiconductor memory device performs a write operation, a read operation, and a scan operation. The write operation is carried out using double-end bit lines, where two bit lines are driven to write data. The read operation is conducted using the double-end bit lines, where two bit lines are driven simultaneously to read data stored in one cell using a sense amplifier (SA) having a latch structure. Alternatively, the read operation is conducted using single-end bit lines, where a single bit line is driven to read data stored in one cell using an SA having a single-inverter structure. The scan operation includes simultaneously reading data stored in bit cells present that are commonly selected by a single word line. In general, this scan operation is carried out using the single-end bit lines and the SA having the single-inverter structure. Japanese Patent Application No. 1999-21712 discloses such a 6T-type semiconductor memory device.
FIG. 1 illustrates a typical bit cell structure 100 of the 6T-type semiconductor graphics memory device, according to the Background Art. Cell structure shown 100 uses a first bit line BL only to write a “0” datum representing a logical low value and a second bit line BLB to write, read, and scan data “1” datum representing a logical high value. As is well known, each of inverters INV1 and INV2 includes two MOSFETs.
Due to characteristics of the 6T-type semiconductor graphics memory device, the single-end bit line cannot be used for the write operation. Instead, the double-end bit line is used in the write operation. In the read operation, either the double-end bit line or the single-end bit line can be used, but it is a common practice to use the single-end bit line in order to reduce chip size and the amount of time required for testing without significantly degrading the speed of the read operation. Similarly, the single-end bit line and the SA having the single-inverter structure are used in the scan operation.
For the scan operation of the 6T-type cell structure 100, when a word line WL is activated, a MOSFET M2 (necessary for the scan operation) and a MOSFET M1 (necessary for a write operation) are turned on at the same time. As a result, undesired power consumption results via the first bit line BL. For the same reason, undesired power consumption results in the read operation as well.
FIG. 2 illustrates a typical bit cell structure 200, according to the Background Art. Bit cell structure 200 is designed to reduce load capacitance of a write bit line in a read/scan operation. Bit cell structure 200 is also designed to reduce undesired power consumption suffered by bit cell structure 100 of FIG. 1. In bit cell structure 200, during a read or scan operation, a write-only word line WL1 is not activated, rather only a read/scan-only word line WL2 is activated. Thus, undesired power consumption during the read or scan operations is reduced.
However, to realize bit cell structure 200, an additional word line is needed relative to bit cell structure 100, which increases chip size. Moreover, when using a divide-word line (DWL) structure to reduce power consumed in the write operation, a different (relative to bit cell structure 100) word line driver circuit to drive write-only word line WL1 and read/scan-only word line WL2 is needed for bit cell structure 200. Also, in terms of a design layout, gates of MOSFETs M1 and M2 of bit cell structure 100 are electrically and physically connect to the same polysilicon word line WL, and thus, MOSFETs M1 and M2 are symmetrical to each other. However, gates of MOSFETs M1 and M2 of bit cell structure 200 are driven by different metallic word lines, i.e., one for write-only word line WL1 and a separate one for read/scan-only word line WL2. As a result, MOSFETs M1 and M2 of FIG. 2 are not symmetrical, which has a drawback of low yield.